Electronic components, such as semiconductor elements, are mounted on wiring substrates. Such a wiring process undergoes a build-up process to increase the density of wiring patterns. Japanese Laid-Open Patent Publication Nos. 2003-023252 and 2003-023253 describe a wiring substrate including a core substrate. A build-up process is performed to stack wiring layers and insulation layers on the upper and lower surfaces of the core substrate.
In such type of a wiring substrate, a solid plane layer (e.g., power supply plane or ground (GND) plane) is formed immediately below an insulation layer to ensure flatness when forming wirings or to match the characteristic impedance. In a wiring substrate including the plane layer, a roughening process is performed on the plane layer to increase the adhesion of the plane layer and the insulation layer that covers the plane layer.